Semiconductor fabrication techniques are constantly improving in order to add complex functionality on smaller wafers with corresponding die sizes. Conventional memory devices are fabricated using technologies such as static random access memory (SRAM) or Flash. Flash memory technology is widely used because of capacity, lower costs, and non-volatility characteristics (i.e., stored data is not lost when a power supply or source to the Flash memory device is turned off). However, there are issues with conventional implementations designed to accommodate increasingly complex memory or logic controller (“controller”) circuitry on a substrate, wafer, or chip (hereafter “chip”).
Conventional memory technologies have restricted die sizes and fabricate separate controller and memory blocks alongside each other on a chip. Complex controller design can also be implemented using multiple processors or additional functionality such as buffer memory, error correction code (ECC), and direct memory access (DMA) hardware for fast movement of data. However, complex controller designs also result in larger die sizes. Another problem with conventional memory technologies is the cost associated with manufacturing and testing separate controller and memory block configurations on the same chip.
Flash memory products require different testing techniques and technologies for controllers and memory blocks. If separate fabrication technologies are used, individually-dedicated testing techniques and facilities are required for the controller and the memory. Separate fabrication and testing techniques and facilities are used with conventional implementations because costs are less than those associated with chips having a combined controller and memory block.
Combined controller and memory designs are expensive to fabricate and test, particularly if the chips are designed to have large memory capacities. An example of a combined controller and memory using Flash technology is developed by M-Systems Incorporated of Sunnyvale, Calif. The controller and memory are combined into a single IC known as a “disk on chip.” However, conventional combined controller-memory implementations such as “disk on chip” suffer from limited capacity due to the combined controller and memory. Conventional combined controller-memory implementations are also inefficient because the logic design for the controller requires additional circuitry to isolate the controller and the memory to allow for independent testing of each block.
There are continuing efforts to improve upon memory and controller designs.